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Pooya is a former semiconductor executive with 28 years of industry experience. After graduating from ¾«¶«Ó°ÊÓ State University, he spent 27 years at Intel Corporation where he held a number of leadership positions within the Assembly & Test Technology Development organization. He was most recently an Intel Fellow and Director of Assembly & Test Pathfinding, where he was responsible for driving Intel's advanced packaging and test roadmap, with a focus on enabling 2.5D/3D ICs, assembly/test solutions for co-packaged photonics, and novel interconnect and thermal technologies for use in test and system applications. Prior to joining ¾«¶«Ó°ÊÓ State, he was VP of Packaging, Test, and Platform engineering at Ayar Labs, working on packaging and test solutions for co-packaged optics. Pooya holds 59 patents, with more than three dozen pending, spanning the fields of test interconnect technology, thermal technology, and package/product architecture.